System-on-chip with ferroelectric random access memory and tunable capacitor
US12225733B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2022 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Nov 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.