Method and apparatus for selecting data access method in a heterogeneous processing system with multiple processors
US12229057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2023 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Apr 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A heterogeneous processing system including a host processor coupled to a host memory, a first processor coupled to a first memory, a second processor coupled to a second memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the host processor, the first processor, the second processor, and the data transfer resources. The host processor is configured to detect an application for execution by both the first processor and the second processor, to select one of multiple data transfer methods for transferring data between the first and second processors, and to configure the heterogeneous processing system based on the selected data transfer method. The data transfer methods include memory extension operation, one memory to memory transfer operation, and two memory to memory transfer operation using at least one intermediate host buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.