Dynamic program caching
US12230334B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2022 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Jul 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller determines that the program operation can be initiated without loading all pages into the memory. In response, the NAND loads a first page and then executes portions of the program operation in parallel, at least in part, with loading subsequent pages. The NAND behavior is modified to monitor data loading completion times, to copy pages from a cache register to a data register as needed, and to resume program operation if a shutdown occurs. The portions of the program operation include a program prologue operation and a pulse verify loop for the first voltage level (L1) of the MLC memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.