Array substrate and display panel
US12230646B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Apr 14, 2022 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Apr 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/451
Abstract
An array substrate and a display panel are provided. The array substrate includes a substrate, a gate, a gate insulating layer, an oxide semiconductor layer, and a source-drain metal layer. Material of at least a portion of the gate insulating layer in contact with the oxide semiconductor layer and material of the oxide semiconductor layer include an oxide of the first metal element. Thus, a transition interface between the gate insulating layer and the oxide semiconductor layer has a lower density of defect states, which is beneficial to improve mobility and stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.