Three dimensional device formation using early removal of sacrificial heterostructure layer
US12230691B2 · kind B2 · utility
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Key dates
| Filing date | May 13, 2022 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | May 24, 2043 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.