Bonded memory device and fabrication methods thereof
US12232316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2020 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Jun 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06524
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a semiconductor device is disclosed. The method includes the following operations. First, an insulating material layer can be formed over a substrate. In an example, single-crystalline silicon is not essential to the substrate. The insulating material layer can be patterned to form an isolation structure and a plurality of trenches in the isolation structure. A semiconductor material can be deposited to fill up the plurality of trenches to form a plurality of array-base regions in the isolation structure, the isolation structure insulating the plurality of array-base regions from one another. Further, a plurality of memory arrays can be formed over the plurality of array-base regions, and an insulating structure can be formed to cover the plurality of memory arrays and the plurality of array-base regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.