Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
US12237368B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2022 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Nov 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/679
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.