Nano-FET transistor with alternating nanostructures and method of forming thereof
US12237399B2 · kind B2 · utility
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11References
20Claims
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Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Sep 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.