In-memory compute array with integrated bias elements
US12243584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2023 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Feb 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.