Forksheet transistors with dielectric or conductive spine

US12243875B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Seung Hoon Sung · Beaverton, US
• Cheng-Ying Huang
• Marko Radosavljevic · Portland, US
• Christopher M. Neumann · Portland, US
• Susmita Ghose · Mountain View, US
• Varun MISHRA · Hillsboro, US
• Cory E. Weber · Portland, US
• Stephen M. Cea · Hillsboro, US
• Tahir Ghani · Portland, US
• Jack T. Kavalieros · Portland, US

Key dates

• Filing date: Jan 10, 2024
• Grant date: Mar 4, 2025
• Expiry date: Jan 10, 2044

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B82Y10/00
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.