ESD protection for multi-die integrated circuits (ICs) including integrated passive devices

US12244137B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Christian Russ · Diedorf, DE
• Kai Esmark · Schwanau, DE

Key dates

• Filing date: May 13, 2022
• Grant date: Mar 4, 2025
• Expiry date: Jun 6, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/931
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The described techniques address issues associated with electrostatic discharge (ESD) protection for multi-die integrated circuits (ICs). The techniques include the use of two or more semiconductor dies within a multi-die IC, which may include a first semiconductor die without ESD protection but with full ESD exposure. The first semiconductor receives ESD protection via a second semiconductor die that is integrated as part of the same package with the first semiconductor die. The second semiconductor die may be electrically more remote from ESD-exposed pins compared to the first semiconductor die. The first semiconductor die may include integrated passive devices. The second semiconductor die enables ESD protection for both semiconductor dies in the same integrated IC package.