Deterministic reset mechanism for asynchronous gearbox FIFOs for predictable latency
US12248761B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Mar 31, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Jun 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein describe a solution for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths. Proposed approaches look for a stable region between read and write clock phases by sweeping one of the clock phases until the leading edges (phases) of both clocks are aligned then releasing the write and read resets deterministically based upon a change in cyclic behavior of detected logic levels of a reset beacon waveform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.