Single plate configuration and memory array operation
US12249362B2 · kind B2 · utility
0Cited by
30References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 10, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Mar 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2257
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.