Memory systems with vertical integration
US12249390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | May 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.