Electronic devices including pillars in array regions and non-array regions

US12250821B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• S M Istiaque Hossain · Boise, US
• Christopher J. Larsen · Boise, US
• Anilkumar Chandolu · Boise, US
• Wesley O. McKinsey · Nampa, US
• Tom J. John · Boise, US
• Arun Kumar Dhayalan · Boise, US
• Prakash Rau Mokhna Rau · Boise, US

Key dates

• Filing date: Dec 20, 2023
• Grant date: Mar 11, 2025
• Expiry date: Dec 20, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/27

Abstract

An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.