Electronic devices in semiconductor package cavities
US12255115B2 · kind B2 · utility
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3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2024 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Mar 26, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19104
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.