Technologies for fabricating a 3D memory structure
US12256558B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2022 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Mar 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) memory structure includes a memory array formed on a side of a substrate, a far-back-end-of-line (FBEOL) structure formed on the memory array, and a back-end-of-line (BEOL) structure formed on another side of the substrate opposite the side on which the memory array and the BEOL structure are formed. Methodologies to fabricate the 3D memory structure are also disclosed and include forming the memory array on the substrate, forming the FBEOL on the memory array, flipping the substrate, and forming the BEOL on the opposite side of the substrate. Alternative 3D memory structures and fabrication methodologies are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.