Method for preparing recessed gate structure with protection layer
US12256565B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Apr 16, 2024 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Apr 16, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure includes a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.