Shared decoder architecture for three-dimensional memory arrays
US12260907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2024 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Mar 29, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.