Sense amplifier architecture providing reduced program verification time
US12260921B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2022 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Dec 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for sensing a data state of a memory cell. In an example implementation, systems and methods disclosed herein perform a method that includes connecting a first sensing node and a second sensing node to a bitline of a sensing amplifier to simultaneously discharge first and second capacitors connected to the first and second sensing nodes, respectively, through the memory cell. After a first sensing period, the second sensing node is disconnected from the bitline, which includes a first voltage level based on discharging the second capacitor. After a second sensing period, the first sensing node is disconnected from the bitline, which includes a second voltage level based on discharging the first capacitor. First and second sensing results are latched based on the first and second voltage levels, respectively, and a data state of the memory cell is based on the first and second voltage levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.