Mold shelf package design and process flow for advanced package architectures
US12261150B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2023 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Dec 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/183
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.