Source/drain epitaxy process in stacked FET
US12262552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2022 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Dec 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
Abstract
Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a first set of nanosheets and a second set of nanosheets on top of the first set of nanosheets, wherein the first set of nanosheets has an uppermost nanosheet and the second set of nanosheets has a lowermost nanosheet, the lowermost nanosheet being separated from the uppermost nanosheet by a first gap; forming a conformal liner covering the first set of nanosheets and the first gap; covering a first portion of the conformal liner at the first gap with a protective stud; selectively removing a second portion of the conformal liner from end surfaces of the first set of nanosheets; and forming source/drain at the end surfaces of the first set of nanosheets. A structure formed thereby is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.