Angled etch to enable tin removal from selected sidewalls
US12266729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2021 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Jul 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit structure comprises depositing an oxide insulator layer over a substrate having fins. A gate trench is formed within the oxide insulator layer with the fins extending above a surface of the oxide insulator layer within the gate trench. A semiconducting oxide material is deposited to conformally cover the oxide insulator layer, including on top surfaces and sidewalls of both the gate trench and the fins. A gate material is deposited to conformally cover the semiconducting oxide material, including on top surfaces and sidewalls of both the gate trench and the fins. An angled etch is performed to remove the gate material selective to the semiconducting oxide material from sidewalls of the gate trench, but not from sidewalls of the fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.