Executing instruction sequences generated from software interactions as part of formal verification of a design under test
US12271669B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2022 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Oct 29, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.