Creating dynamic latches above a three-dimensional non-volatile memory array
US12272421B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Aug 25, 2022 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Jan 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.