Reducing spurious write operations in a memory device
US12272424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Aug 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes bitcells connected to wordlines and bitlines, and driver circuitry that updates the bitcells. The driver circuitry includes first transistors, and a first inverter device. The first transistors drive a bitcell of a memory device. The first inverter device is coupled to the first transistors, and drives the first transistors with a first control signal. The first inverter device includes first inverter circuitry and second inverter circuitry. The first inverter circuitry receives a first signal, a first voltage, and a second voltage differing from the first voltage, and generates a first inverted signal based on the first signal, the first voltage and the second voltage. The second inverter circuitry receives the first inverted signal, the second voltage and a third voltage differing from the second voltage, and generates the first control signal based on the first inverted signal, the third voltage and the second voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.