Patent · US Active

Three-dimensional memory devices and fabricating methods thereof

US12272645B2 · kind B2 · utility

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18Claims
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Key dates

Filing dateMay 6, 2022
Grant dateApr 8, 2025
Priority date
Expiry dateJun 10, 2043

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B12/09
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.