Control gate structures in three-dimensional memory devices and methods for forming the same
US12274055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2022 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Jul 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A method includes disposing a layer stack on a substrate, the layer stack including a number of levels. A first control gate structure is formed in a first level of the number of levels by: forming a first opening through a dielectric layer of the first level and a sacrificial layer of the first level; removing a remaining portion of the sacrificial layer of the first level to form a first cavity; and disposing a first conductive layer in the first cavity. A second control gate structure is formed in a second level below the first level by: extending the first opening into a dielectric layer of the second level and a sacrificial layer of the second level to form a second opening; removing a remaining portion of the sacrificial layer of the second level to form a second cavity; and disposing a second conductive layer in the second cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.