Fabrication method for JFET with implant isolation
US12274086B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Mar 8, 2024 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Mar 8, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/106
Abstract
Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.