Patent · US Active

Peripheral circuit having recess gate transistors and method for forming the same

US12278209B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

Yanwei Shi · 红钢城街道, CN
Yanhong Wang · Beijing, CN
Cheng Gan · Hubei, CN
Liang Chen · 红钢城街道, CN
Wei Liu · 红钢城街道, CN
Zhiliang Xia · 红钢城街道, CN
Wenxi Zhou · 红钢城街道, CN
Kun Zhang · Hubei, CN
Yuancheng Yang · Hubei, CN

Key dates

Filing date	Oct 26, 2021
Grant date	Apr 15, 2025
Priority date	—
Expiry date	Sep 11, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH10B43/27
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.