Semiconductor devices having upper and lower active contacts
US12279449B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2021 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Apr 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Semiconductor devices having improved performance and reliability. For example, a semiconductor device may include a substrate, an active pattern extending in a first direction, on the substrate, a plurality of gate structures on the active pattern, each including a gate electrode that crosses the active pattern. A lower active contact may be connected to a source/drain pattern. A trench may expose the lower active contact, and a width of a bottom surface of the trench in the first direction may be greater than a width of an upper surface of the lower active contact in the first direction. An etching stop film may be along the bottom surface of the trench and side walls of the trench, and have an uppermost surface coplanar with an upper surface of an upper active contact that extends through the etching stop film and is connected to the lower active contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.