Patent · US Active

Array dependent voltage compensation in a memory device

US12283324B2 · kind B2 · utility

0Cited by

5References

14Claims

0Family size

Assignee

Sandisk Technologies, Inc. · US

Inventors

Ke Zhang · Beijing, CN
Liang Li · Shanghai, CN
Ming Wang · Shanghai, CN

Key dates

Filing date	Jun 10, 2022
Grant date	Apr 22, 2025
Priority date	—
Expiry date	Dec 19, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH10B43/50
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.