Edge fin trim process
US12283526B2 · kind B2 · utility
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20Claims
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Assignee
Inventors
Key dates
| Filing date | Nov 8, 2021 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Dec 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structures and methods are provided. In one embodiment, a method of the present disclosure includes forming a plurality of semiconductor fins over a substrate, after the forming of the plurality of semiconductor fins, removing an outer semiconductor fin of the plurality of semiconductor fins, and forming a gate structure over the plurality of semiconductor fins. The plurality of semiconductor fins include more than 3 semiconductor fins and the removing recesses a portion of the substrate directly under the outer semiconductor fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.