Method and system for CMOS-like logic gates using TFTs and applications therefor
US12288520B2 · kind B2 · utility
0Cited by
0References
13Claims
0Family size
Inventors
Key dates
| Filing date | Mar 11, 2022 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Mar 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosure is directed at a CMOS-like logic gate including a set of thin-film transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.