Memory interface and semiconductor memory device and semiconductor device including the same
US12293801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2023 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Jun 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a memory controller configured to provide a data strobe signal, and a memory device configured to receive a data signal provided from the memory controller or output a data signal to the memory controller, wherein the memory device includes a memory interface including a plurality of DQ driving circuits, the memory interface being configured to generate a plurality of phase clock signals based on the data strobe signal, determine a number of phase clock signals provided to the plurality of DQ driving circuits based on an operating frequency of the memory device, and provide the determined number of phase clock signals to the plurality of DQ driving circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.