Memory controller with enhanced low-power state
US12299297B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 29, 2023 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Jun 29, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the configuration data in response to the memory controller completing a save operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.