Method of forming protective layer utilized in silicon remove process
US12300534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2022 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Sep 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.