Systems and methods for analyzing defects in CVD films
US12300554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2023 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Jul 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.