Three-dimensional memory devices and methods for forming the same

US12300648B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Yuancheng Yang · Hubei, CN
• Kun Zhang · Hubei, CN
• Wenxi Zhou · 红钢城街道, CN
• Zhiliang Xia · 红钢城街道, CN
• Liang Chen · 红钢城街道, CN
• Yanhong Wang · Beijing, CN
• Wei Liu · 红钢城街道, CN

Key dates

• Filing date: Sep 22, 2021
• Grant date: May 13, 2025
• Expiry date: Sep 9, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/14511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.