Optimization of a digital pattern file for a digital lithography device
US12302641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2019 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Apr 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital pattern generation system comprises a memory and a controller. The controller is coupled the memory and is configured to remove redundant cells from a digital pattern file, generate a first updated digital pattern file and compare the first updated digital pattern file with the digital pattern file. Further a number of vertexes of a first arc of the first updated digital pattern file is reduced to generate a second updated digital pattern file. Additionally, a first cell of the second updated digital pattern file is replaced with an alternative version of the first cell to generate a third updated digital pattern file. Further, one or more polygons within the third updated digital pattern file is converted to one or more quad polygons to generate an optimized digital pattern file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.