Circuit design having an improved clock tree
US12307187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2022 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Jan 14, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method updates a clock tree based on skew values of the circuit design. The clock tree is updated by obtaining a circuit design that includes circuit elements and a clock tree. The clock tree includes clock sources and clock sinks. Data path slack values for the clock tree are determined based on the clock sources and the clock sinks. Further, clock arrival values for the clock tree are determined based on the clock sources and the clock sinks. A first total local skew value of the circuit design is determined based on the data path slack values, and the clock arrival values, and updating the clock tree based on the first total local skew value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.