Pseudo-2-port memory with dual pre-charge circuits
US12308091B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 7, 2021 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Nov 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit system and method for using the same are provided. In one example, the memory circuit system includes a memory array, a first precharge circuit, and a second precharge circuit. The memory array writes a first set of columns of the memory array. The first precharge circuit charges bitlines of a second set of columns of the memory array while bitlines of the first set of columns discharge. The first set of columns is different from the second set of columns. The second precharge circuit charges the bitlines of the first set of columns after the memory array has finished writing the first set of columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.