TEC-embedded dummy die to cool the bottom die edge hotspot
US12308299B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Dec 22, 2020 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Apr 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N10/17
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein include thermoelectric cooling (TEC) dies for multi-chip packages. In an embodiment, a TEC die comprises a glass substrate and an array of N-type semiconductor vias and P-type semiconductor vias through the glass substrate. In an embodiment, conductive traces are over the glass substrate, and individual ones of the conductive traces connect an individual one of the N-type semiconductor vias to an individual one of the P-type semiconductor vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.