Packaging architecture for disaggregated integrated voltage regulators
US12308362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2021 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Sep 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.