3D semiconductor device and array layout with isolated conductive pillars
US12310023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2023 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Aug 31, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.