Stacked backend memory with resistive switching devices

US12310032B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Wilfred Gomes · Portland, US
• Abhishek A. Sharma · Hillsboro, US
• Van H. Le · Portland, US
• Hui Jae Yoo · Hillsboro, US

Key dates

• Filing date: Jun 8, 2021
• Grant date: May 20, 2025
• Expiry date: Sep 20, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/826

Abstract

IC devices with stacked backend memory with resistive switching devices are disclosed. An example IC device includes a support structure, a frontend layer with a plurality of frontend devices, and a backend layer with a plurality of resistive switching devices, the resistive switching devices being, e.g., part of memory cells of stacked backend memory. For example, the backend layer may implement stacked arrays of 1T-1RSD memory cells, with resistive switching devices coupled to some S/D regions of access transistors of the memory cells. Such memory cells may be used to implement stacked eMRAM or eRRAM, with access transistors being TFTs. Stacked TFT-based eMRAM or eRRAM as described herein may help increase density of MRAM or RRAM cells, hide the peripheral circuits that control the memory operation below the memory arrays, and address the scaling challenge of some conventional memory technologies.