Semiconductor devices including backside vias and methods of forming the same
US12310057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2024 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Jun 13, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76804
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.