Patent · US Active

Method for producing semiconductor wafers

US12313578B2 · kind B2 · utility

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14Claims

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Assignee

Siltronic AG · DE

Inventors

Michael Boy · Waging am See, DE
Ludwig Koester · Burghausen, DE
Elena Soyka · Emmerting, DE
Peter Storck · Mehring, DE

Key dates

Filing date	Apr 30, 2020
Grant date	May 27, 2025
Priority date	—
Expiry date	Feb 11, 2042

Classification

Technology area (CPC C)Chemistry; Metallurgy
CPC primaryC30B15/00
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Suitability of silicon wafers for use in device processing without generation of fatal defects is assessed by using SIRD to measure stress in a wafer cut from a piece of a crystal ingot after first and second thermal treatments of the water, the second thermal treatment consisting of a heating phase, a holding phase, and a cooling phase. The result is used to consider whether silicon wafers cut from the piece can adequately survive device processing without generating excess defects.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.