Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device
US12315573B2 · kind B2 · utility
0Cited by
3References
17Claims
0Family size
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Key dates
| Filing date | Mar 28, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Mar 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.