Delay circuit
US12316326B1 · kind B1 · utility
0Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jul 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00202
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit. In some embodiments, a non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to generate a digital representation of a circuit including: a first inverter, having an input, an output, and two power supply connections; a first current source, electrically coupled in series between a power supply conductor and a power supply connection of the two power supply connections of the first inverter; and a ramp generator circuit, electrically coupled to the input of the first inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.